Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer

ABSTRACT

In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the fabrication ofsophisticated integrated circuits including transistor elementscomprising gate structures on the basis of a high-k gate dielectricmaterial in combination with a metal electrode material.

2. Description of the Related Art

The fabrication of advanced integrated circuits, such as CPUs, storagedevices, ASICs (application specific integrated circuits) and the like,requires the formation of a large number of circuit elements on a givenchip area according to a specified circuit layout, wherein field effecttransistors represent one important type of circuit element thatsubstantially determines performance of the integrated circuits.Generally, a plurality of process technologies are currently practiced,wherein, for many types of complex circuitry including field effecttransistors, CMOS technology is one of the most promising approaches dueto the superior characteristics in view of operating speed and/or powerconsumption and/or cost efficiency. During the fabrication of complexintegrated circuits using, for instance, CMOS technology, millions oftransistors, i.e., N-channel transistors and P-channel transistors, areformed on a substrate including a crystalline semiconductor layer. Afield effect transistor, irrespective of whether an N-channel transistoror a P-channel transistor is considered, typically comprises so-calledPN junctions that are formed by an interface defined by highly dopedregions, referred to as drain and source regions, and a slightly dopedor non-doped region, such as a channel region, disposed adjacent to thehighly doped regions. In a field effect transistor, the conductivity ofthe channel region, i.e., the drive current capability of the conductivechannel, is controlled by a gate electrode formed adjacent to thechannel region and separated there-from by a thin insulating layer. Theconductivity of the channel region, upon formation of a conductivechannel due to the application of an appropriate control voltage to thegate electrode, depends on the dopant concentration, the mobility of thecharge carriers and, for a given extension of the channel region in thetransistor width direction, on the distance between the source and drainregions, which is also referred to as channel length. Hence, theconductivity of the channel region substantially affects the performanceof MOS transistors.

Presently, the vast majority of integrated circuits are based on silicondue to substantially unlimited availability, the well-understoodcharacteristics of silicon and related materials and processes and theexperience gathered during the last 50 years. Therefore, silicon willlikely remain the material of choice for future circuit generationsdesigned for mass products. One reason for the importance of silicon infabricating semiconductor devices has been the superior characteristicsof a silicon/silicon dioxide interface that allows reliable electricalinsulation of different regions from each other. The silicon/silicondioxide interface is stable at high temperatures and, thus, allowsperforming subsequent high temperature processes, as are required, forexample, for anneal cycles to activate dopants and to cure crystaldamage without sacrificing the electrical characteristics of theinterface.

For the reasons pointed out above, in field effect transistors, silicondioxide has been preferably used as a base material of gate insulationlayers that separate the gate electrode, frequently comprised ofpolysilicon or metal-containing materials, from the silicon channelregion. In steadily improving device performance of field effecttransistors, the length of the channel region has been continuouslydecreased to improve switching speed and drive current capability. Sincethe transistor performance is controlled by the voltage supplied to thegate electrode to invert the surface of the channel region to asufficiently high charge density for providing the desired drive currentfor a given supply voltage, a certain degree of capacitive coupling,provided by the capacitor formed by the gate electrode, the channelregion and the silicon dioxide disposed therebetween, has to bemaintained. It turns out that decreasing the channel length requires anincreased capacitive coupling to avoid the so-called short channelbehavior during transistor operation. The short channel behavior maylead to an increased leakage current and to a pronounced dependence ofthe threshold voltage on the channel length. Aggressively scaledtransistor devices with a relatively low supply voltage and thus reducedthreshold voltage may suffer from an exponential increase of the leakagecurrent, while also requiring enhanced capacitive coupling of the gateelectrode to the channel region. Thus, the thickness of the silicondioxide layer has to be correspondingly reduced to provide the requiredcapacitance between the gate and the channel region. For example, achannel length of approximately 0.08 μm may require a gate dielectricmade of silicon dioxide as thin as approximately 1.2 nm. Although,generally, usage of high speed transistor elements having an extremelyshort channel may be substantially restricted to high speed signalpaths, whereas transistor elements with a longer channel may be used forless critical signal paths, such as storage transistor elements, therelatively high leakage current caused by direct tunneling of chargecarriers through an ultra-thin silicon dioxide gate insulation layer mayreach values for an oxide thickness in the range or 1-2 nm that may notbe compatible with thermal design power requirements for performancedriven circuits.

Therefore, replacing silicon dioxide based dielectrics as the materialfor gate insulation layers has been considered, particularly forextremely thin silicon dioxide based gate layers. Possible alternativematerials include materials that exhibit a significantly higherpermittivity so that a physically greater thickness of a correspondinglyformed gate insulation layer provides a capacitive coupling that wouldbe obtained by an extremely thin silicon dioxide layer. It has thus beensuggested to replace silicon dioxide with high permittivity materialssuch as tantalum oxide (Ta₂O₅), with a k of approximately 25, strontiumtitanium oxide (SrTiO₃), having a k of approximately 150, hafnium oxide(HfO₂), HfSiO, zirconium oxide (ZrO₂) and the like.

Additionally, transistor performance may be increased by providing anappropriate conductive material for the gate electrode so as to replacethe usually used polysilicon material, since polysilicon may suffer fromcharge carrier depletion at the vicinity of the interface to the gatedielectric, thereby reducing the effective capacitance between thechannel region and the gate electrode. Thus, a gate stack has beensuggested in which a high-k dielectric material provides enhancedcapacitance, while additionally maintaining leakage currents at anacceptable level. On the other hand, the non-polysilicon material, suchas titanium nitride and the like, in combination with other metals, maybe formed so as to connect to the high-k dielectric material, therebysubstantially avoiding the presence of a depletion zone. Since thethreshold voltage of the transistors, which represents the voltage atwhich a conductive channel forms in the channel region, is significantlydetermined by the work function of the metal-containing gate material,an appropriate adjustment of the effective work function with respect tothe conductivity type of the transistor under consideration has to beguaranteed.

Providing different metal species for adjusting the work function of thegate electrode structures for P-channel transistors and N-channeltransistors at an early manufacturing stage may, however, be associatedwith a plurality of difficulties, which may stem from the fact that acomplex patterning sequence may be required during the formation of thesophisticated high-k metal gate stack, which may result in a significantvariability of the resulting work function and thus threshold of thecompleted transistor structures. For instance, during a correspondingmanufacturing sequence the high-k material may be exposed to oxygen,which may result in an increase of layer thickness and thus a reductionof the capacitive coupling. Moreover, a shift of the work function maybe observed when forming appropriate work function metals in an earlymanufacturing stage, which is believed to be caused by a moderately highoxygen affinity of the metal species, in particular during hightemperature processes which may typically be required for completing thetransistor structures, for instance for forming drain and source regionsand the like.

For this reason, in some approaches, the initial gate electrode stackmay be provided with a high degree of compatibility with conventionalpolysilicon-based process strategies and the actual electrode metal andthe final adjustment of the work function of the transistors may beaccomplished in a very advanced manufacturing stage, i.e., aftercompleting the basic transistor structure.

In a corresponding replacement gate approach, the polysilicon materialacting as a sacrificial or placeholder material is removed afterdepositing at least a portion of the interlayer dielectric material byany appropriate etch techniques. Typically, the interlayer dielectricmaterial may comprise stress-inducing dielectric layers in order tofurther enhance overall transistor performance. It is well known that ahigh strain component in the channel region of silicon-based transistorsmay result in a significant modification of the mobility of the chargecarriers and thus of the overall conductivity of the channel region. Forthis reason a stress-inducing dielectric material may be placed in closeproximity to the transistors in order to provide a desired straincomponent in the channel regions. Since P-channel transistors andN-channel transistors may require a different type of strain component,the stress-inducing dielectric materials may be provided with adifferent internal stress level in order to selectively enhanceperformance of N-channel transistors and P-channel transistors,respectively. The selective provision of an appropriately stresseddielectric material may be accomplished on the basis of a so-called“dual stress liner” approach in which a sequence of deposition andremoval processes in combination with an appropriate masking regime isapplied in order to position, for instance, a tensile stresseddielectric material above an N-channel transistor and a compressivelystressed dielectric material above a P-channel transistor.

Although the above-described replacement gate strategy may be apromising approach, it turns out, however, that deposition-relatedirregularities may be created, in particular in P-channel transistors,the gate electrode structures of which may be embedded in thecompressively stressed silicon nitride material. It is believed that thecompressive stress of the silicon nitride material may result in adisadvantageous shape of the opening that is obtained after the removalof the polysilicon placeholder material. Consequently, upon depositingthe materials required for the replacement gate, such as metals, high-kdielectric materials and the like, the cross-sectional shape of theopening affected by the surrounding compressively stressed dielectricmaterial may result in corresponding irregularities, such as voids andthe like, in particular when an electrode metal is to be filled into theopening. Consequently, in particular in sophisticated semiconductordevices, in which a gate length of approximately 40 nm and less with agate height of approximately 80-100 nm may be required, thedisadvantageous influence of the compressively stressed dielectricmaterial may result in significant yield loss due to voids or any otherdeposition irregularities in the gate electrode structures.

The present disclosure is directed to various methods and devices thatmay avoid, or at least reduce, the effects of one or more of theproblems identified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure provides semiconductor devices andmanufacturing techniques in which a placeholder material of a gateelectrode structure may be replaced by a metal-containing electrodematerial in an advanced manufacturing stage, wherein a tensile stresseddielectric material, that may laterally enclose the gate electrodestructures of any type of transistors, may result in a superiorcross-sectional shape of an opening that is formed after the removal ofthe placeholder material. That is, due to the tensile stress of theadjacent dielectric material, a tapered cross-sectional shape of theresulting opening may be obtained, which thus has an increased lateraldimension at the top of the opening compared to the bottom, therebyenabling a reliable filling in of any appropriate material, such ashigh-k dielectrics if required, metal-containing electrode materials andthe like. On the other hand, the tensile stressed dielectric materialmay also result in a superior transistor performance of, for instance,N-channel transistors, while a negative effect on P-channel transistorsmay be reduced by modifying the intrinsic stress level of the tensilestressed dielectric material above the P-channel transistor by removingthe material, by providing an additional compressively stresseddielectric material and the like. In this manner, an efficientstrain-inducing mechanism may be implemented, such as a modified dualstress liner approach, while nevertheless providing superior depositionconditions when refilling the opening in the gate electrode structure.

One illustrative method disclosed herein comprises forming a tensilestressed dielectric layer above and adjacent to a first gate electrodestructure of a first transistor and above and adjacent to a second gateelectrode structure of a second transistor, wherein the first and secondgate electrode structures comprise a placeholder material. The methodadditionally comprises removing a first portion of the tensile stresseddielectric layer above the first and second gate electrode structures soas to expose a top surface of the placeholder material, while a secondportion of the tensile stressed dielectric material is maintainedlaterally adjacent to the first and second gate electrode structures.Moreover, the method comprises replacing the placeholder material withone or more metal materials in the first and second gate electrodestructures in the presence of the second portion. Additionally, themethod comprises forming a compressively stressed dielectric layer abovethe second gate electrode structure after replacing the placeholdermaterial.

A further illustrative method disclosed herein comprises forming atensile stressed dielectric material so as to laterally enclose a gateelectrode structure of a transistor and to expose a top surface of aplaceholder material of the gate electrode structure. Furthermore, themethod comprises removing the placeholder material in the presence ofthe tensile stressed dielectric material in order to form a taperedopening in the gate electrode structure. The method additionallycomprises filling the opening with one or more materials, at least oneof which represents a metal-containing electrode material. Additionally,the method comprises reducing a strain-inducing effect of the tensilestressed dielectric material on the transistor.

One illustrative semiconductor device disclosed herein comprises a gateelectrode structure of a transistor formed above a semiconductor region.The gate electrode structure comprises a gate insulation layer includinga high-k dielectric material and also comprises an electrode materialthat is formed on the gate insulation layer and has a taperedcross-sectional configuration. The semiconductor device furthercomprises a dielectric material formed above the gate electrodestructure and having an internal compressive stress level so as toinduce a compressive strain in a channel region of the transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIGS. 1 a-1 f schematically illustrate cross-sectional views of asemiconductor device during various manufacturing stages in which a gateplaceholder material may be replaced in an advanced manufacturing stageon the basis of superior cross-sectional shapes of respective gateopenings caused by a tensile stressed dielectric material, according toillustrative embodiments;

FIG. 1 g schematically illustrates a cross-sectional view of thesemiconductor device in a further advanced manufacturing stage in whicha compressively stressed dielectric material may be selectively modifiedin its initial stress level, according to further illustrativeembodiments; and

FIG. 1 h schematically illustrates the semiconductor device according tostill further illustrative embodiments in which the tensile stresseddielectric material, after refilling the gate electrode structures, maybe selectively treated in order to reduce the effect of this material onone type of transistor.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

The present disclosure provides semiconductor devices and manufacturingtechniques in which the refilling of an opening in gate electrodestructures may be performed on the basis of a superior cross-sectionalshape of the opening for any type of transistor, thereby substantiallyavoiding deposition-related irregularities, such as voids, as mayfrequently be encountered in sophisticated semiconductor devices inwhich metal gate electrodes may be provided in combination with a dualstress liner approach. The superior cross-sectional shape of the gateopening may be obtained by providing a tensile stressed dielectricmaterial above the transistor elements and thus laterally adjacent tothe gate electrode structure prior to removing the placeholder material,thereby avoiding the presence of a compressively stressed dielectricmaterial adjacent to gate electrode structures, as may be the case inconventional replacement gate approaches performed after the provisionof differently stressed dielectric materials. Consequently, uponremoving the placeholder material, the tensile stressed dielectricmaterial may act on the sidewalls of the resulting opening, therebyobtaining a tapered cross-sectional shape, which is to be understood asa shape in which a width at the bottom of the gate opening maysubstantially correspond to the initially created gate length, while thelateral extension at the top portion of the gate opening may beincreased. Due to this tapered shape, i.e., the initial gate length atthe bottom and an increased “gate length” at the top of the gateopening, superior deposition conditions may be provided, in particularif gate electrode structures of a designed gate length of approximately40 nm and less are considered. Additionally, the tensile stresseddielectric material may result in an improvement of transistorperformance for one type of transistor, such as N-channel transistors,whereas any negative effect of the tensile stressed dielectric materialon the other type of transistor may be compensated for, or at leastsignificantly reduced, by providing a compressively stressed dielectricmaterial, wherein, depending on the overall process strategy, in someillustrative embodiments, the tensile stress level may be selectivelyrelaxed prior to the deposition of the compressively stressed dielectricmaterial. In other cases, if desired, the tensile stressed dielectricmaterial may be selectively replaced with a compressively stresseddielectric material so that a modified dual stress liner approach mayresult in superior strain conditions in any type of transistor.Consequently, a gradual and uniform tapered cross-sectional shape may beobtained for the gate openings of each type of transistor withoutrequiring sophisticated patterning strategies, for instance by applyingspecifically designed etch techniques during the patterning of the gatelayer stack, which may result in a significantly more complex overallprocess flow. Thus, the replacement gate approach may be efficientlycombined with efficient strain-inducing mechanisms based on stresseddielectric materials, which may enable a further device scaling withoutcontributing to increased yield losses.

FIG. 1 a schematically illustrates a cross-sectional view of asemiconductor device 100 comprising a substrate 101, such as asemiconductor substrate, an insulating substrate and the like, abovewhich may be formed a semiconductor layer 102. The semiconductor layer102 may be comprised of silicon, possibly in combination with otherspecies, such as germanium, carbon and the like, as may be required forforming therein and thereabove circuit elements such as transistors150A, 150B and the like. As previously indicated, crystallinesilicon-based semiconductor materials may preferably be used forsophisticated complex circuitry wherein the electronic characteristics,such as charge carrier mobility and the like, may be efficientlymodified on the basis of creating a specific strain locally in thesemiconductor layer 102, as previously discussed. The semiconductorlayer 102 may have any appropriate thickness, for instance from severalnanometers to a hundred nanometers and more, depending on the overallconfiguration of the semiconductor device 100. For example, insophisticated silicon-on-insulator (SOI) devices, a buried insulatingmaterial (not shown) may be formed directly below the semiconductorlayer 102, wherein a thickness of sophisticated fully depletedtransistor elements may be several nanometers. In other cases, thesubstrate 101 and the semiconductor layer 102 may represent a bulkconfiguration in which the crystalline semiconductor material may extendinto the depth of the substrate 101, which may be significantly greatercompared to a vertical extension of the transistor elements 150A, 150B.Furthermore, it should be appreciated that the semiconductor layer 102may comprise any appropriate isolation structures (not shown) in orderto appropriately laterally delineate semiconductor regions or activeregions, such as regions 102A, 102B, which are to be understood assemiconductor regions having formed therein one or more PN junctions,for instance in the form of source and drain regions 153, which form aPN junction with a channel region 152 laterally enclosed by the drainand source regions 153. In the example shown, the transistors 150A, 150Bmay represent transistors of different conductivity type so that thedrain and source regions 153 may be formed on the basis of dopantspecies of different type wherein, for convenience, any such differencesare not shown in FIG. 1 a. Furthermore, in order to reduce overallcontact resistivity of the drain and source regions 153, frequently,metal silicide regions 154 may be provided in a portion of the drain andsource regions 153. The transistors 150A, 150B may further comprise agate electrode structure 151 comprising a gate insulation layer 151Gthat separates an “electrode” material 151P from the channel region 152.As previously indicated, in a replacement gate approach, at least asignificant portion of the electrode material 151P, which will also bereferred to as placeholder material, may be removed and replaced by ahighly conductive material, such as a metal and the like. In someapproaches, the gate insulation layer 151G, or at least a portionthereof, may also be removed in a further advanced manufacturing stagein order to provide a high-k dielectric material, while in otherapproaches the gate insulation layer 151G may already comprise a high-kdielectric material, possibly in combination with a conductive capmaterial that may provide superior conductivity and that may reliablyprotect the sensitive high-k dielectric material of the gate insulationlayer 151G during the process sequence for forming the transistors 150A,150B and during the process sequence for replacing the placeholdermaterial 151P. For convenience, any such conductive cap layer materialsare not shown in FIG. 1 a. Furthermore, as previously indicated, in someapproaches, a work function adjusting species may have been incorporatedinto the material 151P and/or the material 151G, if consideredappropriate, while in other cases any such work function adjusting metalspecies may be provided upon replacing the placeholder material 151 p.

Furthermore, the gate electrode structure 151 may comprise a spacerstructure 151S, for instance formed on the basis of a silicon nitridematerial in combination with a silicon dioxide etch stop liner (notshown), while in other cases any other appropriate configuration ofspacer elements and etch stop liners may be applied. Furthermore, insome cases, the spacer structure 151S, or at least a portion thereof,may be removed in this manufacturing stage if considered appropriate,for instance in view of enhancing the overall strain-inducing efficiencyof a dielectric material 120, which may be formed above the activeregions 102A, 102B and above the corresponding gate electrode structures151. In the embodiment shown in FIG. 1 a, the dielectric layer 120 maybe provided with an intrinsic tensile stress level, which may result insuperior strain conditions in one of the transistors 150A, 150B, forinstance in the transistor 150A when representing an N-channeltransistor, while the corresponding tensile component may negativelyaffect performance of the transistor 150B and may be compensated for oreven over-compensated for in a later manufacturing process. Thedielectric layer 120 may have any appropriate thickness, as may berequired in view of the overall geometric configuration of the device100. That is, for sophisticated semiconductor devices comprising circuitelements having critical dimensions of approximately 40 nm and less, acomplex surface topography may be created, in particular in denselypacked device regions. For example, the gate electrode structures 151may have a height of approximately 50-100 nm and higher, while a length,i.e., in FIG. 1 a, the horizontal extension of the place-holder material151P, may be 40 nm and less. Consequently, for closely spaced gateelectrode structures and thus conductive lines, corresponding spacingsof approximately 100 nm and less may be created, thereby requiringsophisticated deposition techniques in order to avoid deposition-relatedirregularities, such as the creation of voids in the dielectric materialof the layer 120 and any material that has to be formed thereon.

The semiconductor device 100 as illustrated in FIG. 1 a may be formed onthe basis of any appropriate process strategy for defining the activeregions 102A, 102B, for instance by providing appropriate isolationstructures, such as shallow trench isolations, in combination withimplantation processes performed on the basis of corresponding maskingregimes so as to define the basic conductivity type and dopant level inthe active regions 102A, 102B. Thereafter, the gate electrode structures151 may be formed by providing an appropriate layer stack and patterningthe same, which may require highly sophisticated process techniques forforming appropriate materials, such as high-k dielectric materials, ifprovided in this manufacturing stage, in combination with conventionaldielectrics, such as silicon oxide-based materials and the like,followed by further materials such as a conductive cap layer, ifrequired, and the like, and the placeholder material 151P. Furthermore,additional dielectric cap materials and the like may typically beprovided in this manufacturing stage as is required for the furtherprocessing of the device 100. Based on complex lithography andpatterning strategies, the gate electrode structures 151 may be formedand the further processing may be continued by forming the drain andsource regions 153 in combination with the spacer structure 151S inorder to obtain the desired vertical and lateral dopant profile for theregions 153. It should be appreciated that additional strain-inducingmechanisms may be implemented, for instance in the form of an embeddedsemiconductor alloy in one or both of the transistors 150A, 150B, ifrequired. For example, prior to completing the drain and source regions153 and prior to forming the spacer structure 151S, correspondingcavities may be formed in one or both of the active regions 102A, 102Band these cavities may be refilled with a strain-inducing semiconductoralloy, such as a silicon/germanium alloy and the like. For example, aplurality of appropriate process strategies are well established so asto form a compressive strain-inducing semiconductor alloy in the activeregions of P-channel transistors. Next, any anneal processes may beperformed in order to activate the dopants in the drain and sourceregions 153 and to re-crystallize implantation-induced damage.Subsequently, the metal silicide regions 154 may be formed by applyingany appropriate process regime, wherein, depending on the overallprocess strategy, the placeholder material 151P may have an appropriateconfiguration in order to avoid a silicidation thereof. For instance,the placeholder material 151P may comprise an appropriate cap layer,such as a silicon nitride material and the like. Thereafter, thedielectric layer 120 may be formed, for instance by plasma enhancedchemical vapor deposition (CVD) techniques in which the processparameters may be appropriately selected on the basis ofwell-established recipes in order to obtain the desired materialcomposition and thus the desired intrinsic tensile stress level. Forexample, silicon nitride-based materials may be deposited with a highcompressive stress level of approximately 3 GPa and even higher, andalso a high tensile stress level of 1 GPa and significantly higher maybe achieved upon selecting appropriate process parameters. For instance,by incorporating a more or less pronounced amount of hydrogen into thesilicon nitride-based material, the internal stress level may beefficiently adjusted. Furthermore, a thickness of the layer 120, whichmay range from approximately ten to several tenths of nanometers, may beappropriately selected in order to obtain the desired conformaldeposition behavior for the surface topography under consideration. Inthe embodiment shown, the dielectric layer 120 may be formed “directly”on the transistors 150A, 150B, i.e., on the metal silicide regions 154,and may be directly in contact with the spacer structure 151S and theplaceholder material 151P. In this case, a very efficient transfer ofthe stress component into the channel region 152 may be accomplished. Inother cases, a further material layer, for instance in the form of asilicon dioxide material and the like, may be provided (not shown) so asto act as an etch stop material during a later manufacturing stage whena portion of the material 120 is to be removed from above one of thetransistors 150A, 150B, such as the transistor 150B, for which theintrinsic tensile stress level may be considered inappropriate forobtaining high performance.

FIG. 1 b schematically illustrates the semiconductor device 100 in afurther advanced manufacturing stage in which a fill material 121 may beformed above the tensile stressed dielectric layer 120 in order to fillspaces between adjacent gate electrode structures 151 and other circuitelements. The fill material 121 may represent any appropriate material,such as a polymer material, a conventional dielectric material such assilicon dioxide and the like, which may be deposited with a high degreeof gap filling capability in order to avoid deposition-relatedirregularities. For example, silicon dioxide material may be provided onthe basis of well-established deposition techniques such assub-atmospheric CVD, high density plasma assisted CVD and the like,thereby reliably filling the spaces of even very sophisticated devicegeometries. If desired, the fill material 121 may be planarized, forinstance by chemical mechanical polishing (CMP) and the like, in orderto provide a substantially planar surface that may result in superiorconditions for the further processing of the device 100. In someillustrative embodiments, the fill material 121 may be provided in theform of a tensile stressed dielectric material, which may, for instance,be accomplished by depositing a silicon dioxide material and treatingthe same so as to obtain a tensile stressed level. In furtherillustrative embodiments, the dielectric layer 120 may be provided withany appropriate material composition and with any desired intrinsicstress level, such as a tensile stress level or a substantially neutralstress level, whereas the desired tensile stress may be provided by thefill material 121. For example, the layer 120 may be provided in theform of a very efficient etch stop material, which may reliably protectthe device 100 during the further processing, for instance during theremoval of the fill material 121 and during the deposition andpatterning of further stress-inducing dielectric materials above thetransistors 150A, 150B.

FIG. 1 c schematically illustrates the semiconductor device 100 during aremoval process 103, such as a CMP process, an etch process or anycombination thereof, during which a top surface 151F of the placeholdermaterial 151P may be exposed in the gate electrode structures 151. Forexample, the removal process 103 may be provided in the form of a CMPprocess for planarizing the fill material 121, wherein a selective CMPrecipe may be applied so as to stop on the layer 120. Thereafter, afurther non-selective CMP recipe may be used in order to commonly removeportions of the material layers 121 and 120, thereby exposing thesurface 151F. It should be appreciated that other techniques may beused, for instance an etch process, possibly in combination with a CMPprocess, depending on the selected process strategy. Furthermore, ifdesired, the removal process 103 may comprise a selective etch processfor removing the fill material 121 when the presence thereof isconsidered inappropriate for the further processing. In other cases, thefill material 121 may be maintained so as to provide superior processconditions during the further processing, i.e., the removal of theplaceholder material 151P and the subsequent deposition of one or moreelectrode materials, as will be described later on in more detail.

FIG. 1 d schematically illustrates the semiconductor device 100 whenexposed to an etch ambient 104, which may be applied on the basis ofappropriate process conditions so as to remove the placeholder material151P (FIG. 1 c) selectively to the spacer structure 151S, the dielectriclayer 120 and the fill material 121, if still present. For this purpose,any appropriate etch recipes may be used, such as wet chemical etchrecipes for removing silicon material selectively with respect tosilicon nitride and silicon dioxide-based materials, which may beaccomplished on the basis of TMAH (tetra methyl ammonium hydroxide),which exhibits a high etch rate for silicon material with a highselectivity with respect to silicon nitride and silicon dioxide and alsoother materials such as titanium nitride and the like. In other cases,other hydroxide solutions may be applied in order to efficiently removea silicon material selectively with respect to silicon nitride andsilicon dioxide. Also, plasma assisted etch recipes may be applied sincehighly selective recipes for removing silicon selectively to silicondioxide and the like are available. Consequently, during the etchprocess 104, an opening 151O may be formed in the gate electrodestructures 151, wherein the opening 151O may extend down to the gateinsulation layer 151G, possibly in combination with a conductive capmaterial, when the high-k dielectric material has been provided in anearlier manufacturing stage upon patterning the gate electrodestructures 151. In other cases, the gate insulation layer 151G, or atleast a portion thereof, may also be removed during the process sequence104 when a high-k dielectric material is to be deposited in a subsequentmanufacturing stage.

Upon forming the opening 151O, the tensile stress component in the layer120 and/or in the fill material 121, if still present, may significantlyaffect the cross-sectional shape of the gate electrode structure 151,thereby generating a tapered cross-sectional shape, which is to beunderstood that, at least in a length direction, i.e., in FIG. 1 d, thehorizontal direction, an increased lateral dimension 151T at the top ofthe opening 151O is obtained. That is, the mechanical effect of thetensile stress component may result in a significantly more pronouncedresponse of the remaining gate electrode structure 151 compared to thebottom of the opening 151O in which the initial gate length 151L may besubstantially maintained due to the adhesion to the underlying activeregions 102A, 102B.

FIG. 1 e schematically illustrates the semiconductor device 100 in afurther advanced manufacturing stage. As illustrated, a gate electrodestructure 151A may be formed in the transistor 150A and may comprise oneor more appropriate electrode materials 151E in order to obtain thedesired work function and thus threshold of the transistor 150A incombination with a high capacitive coupling based on the gate insulationlayer 151G, which may comprise a high-k dielectric material, aspreviously explained. Similarly, the transistor 150B may comprise a gateelectrode structure 151B comprising one or more electrode materials 151Din order to provide the required work function and thus thresholdvoltage for the transistor 150B. It should be appreciated that the gateelectrode structures 151A, 151B may comprise a high-k dielectricmaterial adjacent to or within the electrode materials 151E, 151D,depending on the overall process strategy, for instance if a high-kdielectric material has to be provided in this manufacturing stage.Furthermore, conductive barrier materials or etch stop materials may berequired for providing different types of metal species in the gateelectrode structures 151A, 151B, depending on the selected processstrategy. For convenience, any such details are not shown in FIG. 1 e.

The gate electrode structures 151A, 151B may be formed on the basis ofany appropriate process strategy, wherein, however, at any rate, thetapered configuration of the opening 151O (FIG. 1 d) provides superiordeposition conditions for forming any type of material layer, such as ahigh-k dielectric material layer, etch stop or barrier layers, and inparticular for filling in an appropriate metal material. For example,one or more materials may be deposited first in order to adjust thedesired work function for the gate electrode structure 151A, wherein acorresponding etch stop material may then be patterned in order toenable an efficient removal of these materials from the gate electrodestructure 151B, which may subsequently receive an appropriate metalspecies for adjusting the desired gate characteristics. If required, afurther metal material may be deposited. Consequently, during thevarious deposition and also removal processes, the previously obtainedsuperior tapered configuration may result in superior process uniformityand thus reliability in adjusting the desired transistorcharacteristics. Furthermore, any excess materials previously depositedmay be efficiently removed by, for instance, CMP when the fill material121 is still in place, while in other cases appropriate masking regimesand etch strategies may be applied. Consequently, the gate electrodestructures 151A, 151B may represent sophisticated metal-containing gatestructures with a high-k dielectric material provided in the gateinsulation layer 151G, wherein the electrode materials 151E, 151D mayhave a tapered cross-sectional configuration according to the differentlength dimensions 151T at the top and 151L at the bottom of the gateelectrode structures 151A, 151B. Hence, the length 151L may representthe actual gate length and may substantially correspond to the desireddesign gate length. Moreover, the material 120 and/or the material 121may induce a desired tensile strain component 152T in the channel region152 of the transistors 150A, 150B.

FIG. 1 f schematically illustrates the semiconductor device 100 whereina further dielectric layer 130 may be formed above the transistors 150A,150B with a desired high compressive stress level. In the embodimentshown, the dielectric layer 130 may be formed above the material 120after removing the fill material 121 (FIG. 1 e), while in other cases(not shown) the layer 130 may be provided on the basis of the deviceconfiguration as shown in FIG. 1 e, i.e., the layer 130 may be formedabove the fill material 121. As previously discussed, siliconnitride-based materials, nitrogen-containing silicon carbide materialsand the like may be formed with a high intrinsic compressive stresslevel, which may thus compensate for or even over-compensate for thestress level of the layer 120, for instance in the transistor 150B,whereas, in the transistor 150A, the stress level may be modified, aswill be explained later on in more detail, while in other cases thematerial 130 may be selectively removed from above the transistor 150A.Consequently, an efficient strain adjustment for both transistors 150A,150B may be accomplished on the basis of the materials 120 and 130without unduly affecting the process of forming the replacement gates151A, 151B. In other illustrative embodiments (not shown), the layer 120may represent a substantially stress neutral material, as alsopreviously discussed, and the strain mechanism may be implemented on thebasis of the material 130 in combination with a further stress-inducingmaterial, thereby implementing a dual stress liner approach, which maybe performed on the basis of the material 120 acting as an efficientetch stop material. On the other hand, the desired superior shape of theelectrode structures 151A, 151B may have been achieved on the basis ofthe fill material 121 (FIG. 1 e), which may be provided with a desiredtensile stress level.

FIG. 1 g schematically illustrates the semiconductor device 100 in afurther advanced manufacturing stage in which a mask 105, such as aresist mask, may be provided in order to cover the layer 130 above thetransistor 150B while exposing a portion 130A of the layer 130 above thetransistor 150A. Moreover, the device 100 may be exposed to a stressrelaxation process 106, for instance performed as an ion implantationprocess, thereby significantly reducing the intrinsic stress level ofthe portion 130A. For example, the process 106 may be based on an ionbombardment using species such as xenon, germanium and the like, whichmay result in a significant modification of the molecular structure andthus may result in a relaxation of the initial intrinsic stress level.Consequently, the layer 120 may still provide a desired tensile straincomponent in the transistor 150A, while the layer 130 formed above thetransistor 150B may compensate for or over-compensate for the tensilestress component of the layer 120. Thereafter, if desired, any furtherstrain-inducing dielectric materials may be deposited if consideredadvantageous.

FIG. 1 h schematically illustrates the semiconductor device 100according to further illustrative embodiments in which the effect of thelayer 120 on the transistor 150 b may be reduced. For this purpose, amask 107, such as a resist mask or any other appropriate mask material,may be provided so as to cover the transistor 150A while exposing thetransistor 150B. Based on the mask 107, in some embodiments, a process108 may be applied in order to selectively reduce or relax the intrinsicstress level of the layer 120, for instance by using an ion bombardmentand the like. Consequently, upon providing a further stress-inducingdielectric material, such as the layer 130 (FIG. 1 g), a very efficientstrain-inducing mechanism may be implemented in the transistor 150B dueto the stress relaxation in the exposed portion of the layer 120. Inother illustrative embodiments, the process 108 may represent an etchprocess for selectively removing the exposed portion of the layer 120,which may be accomplished, for example, on the basis of an etch stoplayer 122, such as a silicon dioxide material and the like, therebyenabling superior process control of the etch process 108. Consequently,after the removal of the exposed portion of the layer 120 selectivelyfrom above the transistor 150B, a compressively stressed dielectricmaterial such as the layer 130 (FIG. 1 g) may be deposited so as to bein close contact to the transistor 150B. If desired, this additionalcompressively stressed dielectric material may be relaxed selectivelyabove the transistor 150A, as is, for instance, previously describedwith reference to the layer 130, while in other cases this portion maybe removed, for instance by providing an etch stop material prior todepositing the compressively stressed material and/or by performing atime controlled etch process. Consequently, also in this case, anefficient dual stress liner approach may be applied for an efficientstrain patterning for the transistors 150A, 150B.

As a result, the present disclosure provides semiconductor devices andmanufacturing techniques in which the deposition conditions uponreplacing a placeholder material of sophisticated gate electrodestructures may be enhanced by generating a substantially continuouslytapering configuration of an opening obtained after the removal of theplaceholder material. To this end, a tensile stressed dielectricmaterial may be provided laterally adjacent to the gate electrodestructure, which may, in some illustrative embodiments, also be used forobtaining a tensile strain component in one type of transistor, such asN-channel transistors. On the other hand, the strain level in othertransistors, such as P-channel transistors, may be adjusted on the basisof a compressively stressed dielectric material, which is thus appliedafter refilling the gate electrode structures with an appropriate metalspecies. Consequently, deposition-related irregularities insophisticated replacement gate approaches may be reduced orsubstantially avoided while nevertheless providing an efficientstrain-inducing mechanism for transistors of different conductivitytype.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Accordingly, the protection sought herein is as set forth inthe claims below.

1.-19. (canceled)
 20. A semiconductor device, comprising: a gateelectrode structure of a transistor formed above a semiconductor region,said gate electrode structure comprising a gate insulation layerincluding a high-k dielectric material and an electrode material formedon said gate insulation layer and having a tapered cross-sectionalconfiguration; and a dielectric material formed above said gateelectrode structure and having an internal compressive stress level soas to induce a compressive strain in a channel region of saidtransistor.
 21. The semiconductor device of claim 20, further comprisinga second gate electrode structure of a second transistor formed above asecond semiconductor region, wherein said second gate electrodestructure comprises a gate insulation layer including a high-kdielectric material and an electrode material formed on said gateinsulation layer and having a tapering cross-sectional configuration andwherein a second dielectric material having a tensile stress level isformed above said second semiconductor region.
 22. The semiconductordevice of claim 20, wherein a length of said electrode material at saidgate insulation layer is approximately 30 nm or less.
 23. Thesemiconductor device of claim 20, further comprising a silicon andnitrogen-containing stress-relaxed dielectric material formed betweensaid gate electrode structure and said dielectric material having saidcompressive stress level.
 24. The semiconductor device of claim 23,wherein at least a portion of said silicon and nitrogen-containingstress-relaxed dielectric material further comprises at least one ofxenon or germanium.
 25. The semiconductor device of claim 23, wherein atleast a portion of said silicon and nitrogen-containing stress-relaxeddielectric material is formed in said dielectric material.
 26. Thesemiconductor device of claim 21, further comprising a third dielectriclayer formed between the first and second dielectric layers and abovesaid semiconductor region and said second semiconductor region.
 27. Thesemiconductor device of claim 26, wherein said third dielectric layercomprises a tensile strain.
 28. The semiconductor device of claim 20,further comprising: a second gate electrode structure of a secondtransistor formed above a second semiconductor region, wherein saidsecond gate electrode structure comprises a gate insulation layerincluding a high-k dielectric material and an electrode material formedon said gate insulation layer and having a tapering cross-sectionalconfiguration; and wherein said dielectric material is formed above saidsecond gate electrode structure.
 29. The semiconductor device of claim28, further comprising a second dielectric layer with a tensile strain.30. The semiconductor device of claim 29, wherein said second dielectriclayer comprises a portion in which said tensile strain isstress-relaxed.
 31. The semiconductor device of claim 28, furthercomprising a silicon and nitrogen-containing stress-relaxed dielectricmaterial formed between said first gate electrode structure and saidfirst dielectric material having said compressive stress level
 32. Asemiconductor device, comprising: a first gate electrode structure of atransistor formed above a first semiconductor region, said first gateelectrode structure comprising a first gate insulation layer including afirst high-k dielectric material and a first electrode material formedon said first gate insulation layer and having a tapered cross-sectionalconfiguration; a second gate electrode structure of a second transistorformed above a second semiconductor region, wherein said second gateelectrode structure comprises a second gate insulation layer including asecond high-k dielectric material and a second electrode material formedon said second gate insulation layer and having a taperingcross-sectional configuration; a first dielectric material formed abovesaid first and second gate electrode structures and having an internalcompressive stress level so as to induce a compressive strain in achannel region of said first transistor; and a second dielectricmaterial formed above said first and second semiconductor regions andlaterally adjacent to said first and second gate electrode structures,said second dielectric material having a tensile stress level so as toinduce a tensile strain in a channel region of said second transistor.33. The semiconductor device of claim 32, wherein a length at least oneof said first and second electrode materials at said respective firstand second gate insulation layers is approximately 30 nm or less. 34.The semiconductor device of claim 32, further comprising a silicon andnitrogen-containing stress-relaxed dielectric material formed betweensaid first gate electrode structure and said first dielectric material.35. The semiconductor device of claim 34, wherein at least a portion ofsaid silicon and nitrogen-containing stress-relaxed dielectric materialfurther comprises at least one of xenon or germanium.
 36. Thesemiconductor device of claim 35, wherein forming said at least aportion of said silicon and nitrogen-containing stress-relaxeddielectric material comprising at least one of xenon or germaniumincludes performing an ion implantation process.
 37. The semiconductordevice of claim 34, wherein at least a portion of said silicon andnitrogen-containing stress-relaxed dielectric material is formed in saidfirst dielectric material.
 38. The semiconductor device of claim 32,further comprising a third dielectric layer formed between the first andsecond dielectric layers and above said first semiconductor region andsaid second semiconductor region.
 39. The semiconductor device of claim37, wherein said third dielectric layer comprises a tensile strain. 40.The semiconductor device of claim 32, wherein said second dielectriclayer comprises a stress-relaxed portion.